RUN 2B L1CAL MEETING MINUTES 21 October, 2004 Present o Fermilab M.Adams, S.Lammers, G.Pawloski, S.Rapisarda, A.Stone, N.Varelas, H.Weerts o MSU D.Edmunds o Nevis H.Evans o Northeastern E.Barberis, D.Wood o Rice P.Padley News (H.Evans) ---- o TAB/GAB Production Readiness Review - held on Oct. 7 at Nevis . Committee: B.Hirosky (chair), I.Bertram, D.Edmunds, J.Steinberg - final report now sent to Vivian . generally quite happy with the project . recommends that we proceed with the assembly of the TABs and GABs! - We have started the orders for this moving through Columbia - Thanks to all those who helped make this project a success and to the members of the committee o Trigger Simulation Workshop tomorrow (Oct. 22) - see agenda posted off of D0 agenda server - main (L1Cal) topic: studies of the EM algorithm . need to make the choice of the geometry of the algorithm in the next week or two Nevis: TAB/GAB (H.Evans) -------------- o Oct. 7 visit by Dan Edmunds and Philippe Laurens to Nevis - went over (face-to-face) all issues of ADF-to-TAB data transmission - grounding of LVDS transmission lines (see below) - data synchronization, especially assigning the correct BX/TURN to data on the TABs . this is done internally on the TAB using a local counter . the counter needs to be initialized on receiving first data from the ADF so that it corresponds to the BX on which the data was *produced* - not the current BX from the SCL . architecture exists to do this in the TABs > needs the exact value of the initial count > may need to be optimized o Grounding Tests for ADF-to-TAB data transmission - have now made direct measurements of LVDS signal quality at the TAB for various grounding schemes for the cable shield . using test board containing a Channel Link Transmitter like on the ADF - possibilities . at ADF a. shield tied directly to ground . at TAB a. leave connection of shield open at TAB end b. connection to ground through resistor and/or capacitor - Signal quality is reasonable in all cases, but best option is clearly a. (shield left open on TAB side) - Tests (will be) documented on L1Cal Hardware page o Latency Measurement of TAB output to Cal-Track - Previous estimate of total amount of latency in TAB ~ 720 ns . measured from arrival of ADF signal at TAB to output of SLDB - New *measurement* with a scope . test input to TAB algo to pulse input to SLDB ~ 450 ns - Estimates for unmeasured bits . input signal retiming (few 60MHz clks) ~ 50 ns . (meas) SLDB latency = 90 ns - TOTAL 590 ns . safely below original estimate - Note: if we change the EM algorithm then this will change as well o Firmware for And/Or terms in GAB - have started coding up the basic list on the web MSU: ADF v2 (D.Edmunds) ----------- o Parts Ordering - being finished up by Jason - Maxim DAC not available in a short time - replaced with a Linear Tech. part (functionally equivalent) - everything else is in hand (except for one oscillator which has been ordered) o Firmware - have used separate designs for "testing" and "physics" operation o Layout - still a few traces left to route, but essentially done . changes for new DAC have been made . more cap's added for a more robust power distrib. - will need to take a day to install new licenses on system o PCB fab - talking with two different companies now - seem ok . the company MSU previously used went out of business o Assembly - not yet started this order - will start looking into it next week o Have discussed with Denis - how to test new SCLD with ADF v2 - using Sacaly's ADF output tester - will be very helpful UIC: Cabling (A.Stone) ------------ o BLS to pleated foil impedance matching may be problematic - seems that pleated foil is 130 Ohms . note: spec's say 80 Ohms > 80 Ohms = conductor working against shielding structure - need to check with Fogelsong o Mock-up of patch panel - current design (for patch panel) seems to work - documentation in progress . have done this test using scrap BLS cables . have a plan for dressing cables in the MCH o ADF backplane end - strain relief is the issue TWG: (S.Rapisarda) ---- o The main components from Agilent have arrived - could perhaps be used in short term as a signal generator for cable tests o Waiting for a few more of the components - one multi-plexer card is missing (should be shipped on Nov. 7) - plus a few more small components for adapter to ADF backplane Simulation (E.Barberis) ---------- o Tomorrow's goal: settle on EM algorithm framework o Interfacing simulator w/ trigsim (by Wendy) - work on this will ramp up after the fall semester