RUN 2B L1CAL MEETING MINUTES
                   18 November, 2004

Present 
o Fermilab      T.Adams, M.Camuyrano, H.Evans, S.Lammers, J.Mitrevski,
                G.Pawloski, S.Rapisarda, N.Varelas
o MSU           C.Brock, D.Edmunds, P.Laurens
o Northeastern  E.Barberis, D.Wood
o Saclay        D.Calvet


Fermilab: TWG (S.Rapisarda)
-------------

o All hardware in place except for adapter
  - easy to put together as soon as needed

o Dan will need this at MSU in first week December



MSU: ADF v2 (D.Edmunds)
-----------

o 10 Cards ready to be fabricated/assembled
  - 5 days turn around time

o Need to know
  - analog input signals: need to know value for termination resistors
    to ground for receiving signals from  cable transition system
  - what fraction of signal makes it through cable transition system

o Answers from Mario
  - system impedance ~ 72 Ohms
  - signal loss fraction ~ 10-15%
  - (these are posted on the web)
  - need to have stamp of approval from John Anderson that these
    numbers are accurate
    . need ~0.5% accuracy
    . Mario will produce a written document for this

o Online Software
  - working on software for testing ADF v2 + long-term software
    . platform independence
    . GUIs
    . FPGA programming

o Crates
  - all ordered - delivery early Dec.


Saclay: ADF (D.Calvet)
-----------

o Denis has various hardware that he can ship to the States
  - what to do with this?
  - Dan suggests that Denis keeps all the hardware (except for 1 SCLD)
    at Saclay in case we need to go there to compare boards



UIC: Cabling (M.Camuyrano)
------------

o Testing essentially done
  - should make final measurements of BLS cable impedances

o Note describing system is being prepared (~1 week)

o Installation
  - John Anderson prefer leaving racks in MCH and swapping cards
  - this is default solution right now
  - estimates 2-3 weeks for this



Nevis: TAB/GAB (H.Evans)
--------------

o GAB Firmware
  - implementing and/or terms on web
  - still needs to be simulated and tested in hardware

o TAB Firmware
  - based on discussions with Dan are implementing a new scheme for
    synchronization of ADF signals at TAB
    . will not require SCL init to sync
    . will resync if BX number inconsistent

o TAB/GAB component ordering
  - still waiting for Columbia purchasing 

o TAB-->DAQ test
  - schedule this for 1st week of Dec. when Dan is at Fermilab

o Long-term ADF-->TAB
  - 


Unpacking: (T.Adams)
----------

o Working toward having data and MC use same unpacker
  - need to define a data format

o Tools available now
  - hex dump that unscrambles VRB channels



Simulation (S.Lammers)
----------

o See Run IIb Trigger Simulation workshop tomorrow