RUN 2B L1CAL MEETING MINUTES 12 July, 2005 Present o Fermilab L.Bagby, J.Benitez, M.Cwiok, D.Edmunds, G.Ginther, S.Lammers, M.Mulhearn, Md.Maimuddin, V.O'Dell, G.Pawloski, P.Renkel, A.Stone, N.Varelas o FSU T.Adams o MSU M.Abolins, J.Biehl, P.Laurens o Nevis H.Evans, C.Johnson (apologies to those I couldn't see) MSU: ---- o Online Software (P.Laurens) - working on Linux application of control software . Philippe will work on this at Fermilab later this week - integration of TAB control software into existing interface . will do a first test this week - start on a document for how to program L1Cal through COOR - discuss how to incorporate the readout crate into this Nevis: TAB/GAB (H.Evans) -------------- o Measurements of clock and data quality for G-Link transmission continue - web page set up with (some of) the results http://www.nevis.columbia.edu/~evans/l1cal/ --> Columbia --> Testing --> G-Link Output Measurements o Plan to provide several possible solutions to loss of sync problem on G-Links at Fermilab. Details below. 0) Sent (today) new 53MHz oscillators to Fermilab for installation on the VME/SCL card (replacing current noisy local oscillator). This will allow tests to be made with a "verified" clock. 1) We have submitted a small G-Link Receiver Test Board for fabrication yesterday. This board will allow us to check for loss of sync and for parity errors on the optical output of the TAB (or GAB) as well as providing lots of test points for examination and/or triggering. This will give us definitive information on Sync/BERs at Nevis and also at Fermilab. (We will make several cards - so one can be sent to Fermilab for tests there.) We can get this board fabricated with a 5 day turnaround and will assemble it at Nevis. So it should be available very soon. 2) We have come up with a slightly modified layout for the VME/SCL board that will allow us to use several different clock distribution schemes (including 53MHz direct to the TAB chip, as suggested by Marvin). The options we foresee are: a) Clean up the original CLK7 path, as transmitted to the TAB over the VME/SCL LVDS cable. This involves removing a redundant PLL and making sure that the signals are transmitted on board using differential PECL. This should be sufficient to take care of any problems that we currently see. b) In case that's not enough, we are also adding a new, dedicated output cable, carrying CLK53 in differential PECL to all the TABs and the GAB. This transmission scheme is as good as you can do and will allow us to avoid multiplying up the clock used for g-link transmission on the TABs and GAB. This new version VME/SCL is ready to be submitted as soon as final checks are made on it. Again, we'll get it with 5-day turnaround and will assemble it in house. 3) At the TAB the new cable will plug into unused pins on the front panel connector that also contains the TAB-to-GAB cable. To get the new signal to the FPGA responsible for sending data to the G-Link (Chip-10 in TAB-speak) we will need to make a tiny daughterboard that plugs into conveniently located test points connected to Chip-10. (Remember that Chip-10 is a BGA, so we can't just add a wire.) This CLK53 from Chip-10 will then drive the g-link transmission. 4) If this doesn't work, we can bypass Chip-10 completely and send the new CLK53 signal from the VME/SCL directly to a pin on the g-link transmitter. Again though, a small daugthercard will have to be made to allow the new CLK53 to get to Chip-10 for purposes of constructing data words, even though Chip-10 will not be responsible for driving the g-link clock. 5) Modifications to the GAB will have to be made to allow the new CLK53 cable to plug into it. We were planning on making a few more of these cards anyway (correcting a few errors related to clock distribution.) We would propose to hold off on submitting the new GABs until we have little more information. The GAB currently at Fermilab will not be very useful for L2/L3 tests but should work fine for everything else. BLS-to-ADF Transition System (A.Stone) ---------------------------- o Ready to go ahead and release order for the rest of ATC (ADF Transition Card) - ADF-to-TAB (via ATM) pseudo-random data transmission tests ran today for several hours w/out parity errors - also tested extensively at MSU - req approved today BLS System Testing (J.Benitez) ------------------ o see slides linked off agenda o Testing System will be left at Fermilab for installation o Addition to Definition of a "Good Set" - Note: these are tested one set at a time - should probably add a basic ADF-to-TAB test into the definition of a Good Set o Fermilab Transition System Test Card - being made in parallel - layout review today - this is a continuity tester - based on Glenair system . checks for shorts/disconnects in the Transition System . note: shorting inputs of an ADF should not cause problems for the card o Need to incorporate this testing plan into the overall integration/installation scheme - make sure that we're not stressing connectors by plugging/unplugging too many times - also do not want to monopolize the Test Stand for long periods of time Pulser Status (P.Renkel) ------------- o Interesting effects observed with the new Pulser system recently - cross-talk: manifests itself as TTs firing when they should not for input pattern . being studied - more info next time o Pulser Patterns - new feature of GUI: shows which TTs should fire for each pattern o Will be installed online next week - in normal use by shifters Test System (L.Bagby) ----------- o see slides posted off agenda o Daily "Toolbox" Meetings started this morning - 9:00am in the DAB1 lunch room - everyone is encouraged to attend G-Link Tests at Fermilab (M.Mulhearn) ------------------------ o see scope trace linked off agenda o Diagnosing the problem (loss of sync after ~1000 L1A's) - examine DAV at transmitter and receiver - look for shifts - spectrum analysis of transmitter and receiver . can give input for tuning G-Link chip parameters - special TAB firmware that continuously sends out 101010.... on the G-Link - better local oscillators for VME/SCL card