Updated: 31-Jul-03
| T1: CS_BMn (pci3_lt) | T2: CS_SCLFn (pci3_lt) | T3: CS_TRDFn (pci3_lt) |
| T4: ENW_L3Data (trdf_format) | T5: Mon_INT (bm_regs) | T6: SCL_INT (bm_regs) |
| T7: EN_MonOn (trdf_regs) | T8: l_DCLK (pci3_cf) | T9: l_nSTATUS (pci3_cf) |
| T10: Strobe_Message (bm_meout) | T11: PUT_DONE (bm) | T12: PUT_DONEn (bm) |
| T13: GET_DONE (bm) | T14: GET_DONEn (bm) | T15: Mon_Start (bm_regs) |
| T16: SCL_Ready (trdf) | T17: EN_SCL_RST (bm_regs) | T18: BM_TP1 (bm_meout) |
| T19: TRDF_L1Err (trdf_format) | T20: R_BM_Mon (sclf_logic) | T21: BM_STROBEn (sclf_logic) |
| T22: TRDF_STROBEn (sclf_logic) | T23: SCL_S0n (sclf_logic) | T24: SCL_S1n (sclf_logic) |
| T25: SCL_S2n (sclf_logic) | T26: PCI1_TP1 (lm_logic) | T27: R_SCLF_Mon (trdf_regs) |
| T28: Test/DAQ (trdf_regs) | T29: ENW_PCI12FIFO (pci2) | T30: EN_TestDelay (test_data) |
| T31: LinkRDYn (trdf_rr) | T32: DAVn (trdf_rr) | T33: CAVn (trdf_rr) |
| T34: CPU_Clr_Mon (bm_regs) | T35: R/W (pci3_lt) | T36: EN_Transfer (pci3_lt) |
| T37: SLV_DONEn (bm_l2) | T38: SLV_RDYn (bm_l2) | T39: DB_L3_Data (pci3_l3) |
| T40: l_CONF_DONE (pci3_cf) | T41: PCI3_TP3 (pci3_tets) | T42: PCI3_TP2 (pci3_cf) |
| T43: PCI3_TP1 (pci3_tets) | T44: TRDF_TP1 (trdf_rr) | T45: TRDF_TP2 (trdf_rr) |
| T46: PCI1_TP2 (lm_logic) | T47: PCI1_TP3 (lm_logic) | T48: PCI2_TP1 (trdf_rr) |
| T49: PCI2_TP2 (lm_logic) | T50: PCI2_TP3 (lm_logic) | T51: SCLF_TP1 (sclf_logic) |
| T52: SCLF_TP2 (test_data) | T53: BM_TP2 (bm_test_pins) |