Instructions for Using the FRC and BC Firmware

Updated: 03-Jun-04

Locations of Firmware Code

Using the FRC Firmware

A. FRC PCI Interfaces (1,2,3)

There are two options here.

1. This firmware is burned onto two prom's that are socketed on the FRC from which it is loaded into the three PCI FPGA's at power-up. (See FRC Layout for locations.)
2. The firmware is loaded to the three FPGAs using the Jtag connector on the FRC via a ByteBlaster connection.

Option a) - proms
To create the pof files to be loaded on the proms do the following.

• After compiling changes to the code: File --> Convert SRAM object
• Select FCF file: Altera\FCF\frc_pci.fcf
  The file order should be (use full pathnames - only shown from Altera\ sub-dir):
  1. pci3_frc\pci3_frc.sof (device = EPC10K50EQC240-1)
  2. pci_2\pci_2.sof (device = EPC10K30EQC208-1)
  3. pci_1\pci_1.sof (device = EPC10K30EQC208-1)
• Output file: pof\frc_pci.pof (device = EPC1PC8)
  Running this will result in two files:
  1. pof\frc_pci.pof --> prom-1
  2. pof\frc_pci_1.pof --> prom-2
• Burn the proms: EPC2LC20
• Seat the proms in their sockets
  • frc_pci.pof --> upper socket
  • frc_pci_1.pof --> lower socket
• Set jtag/prom DIP switches to all "1"'s

B. FRC Logic

The FRC logic consists of firmware for the TRDF, BM and SCLF FPGAs. It is loaded to the chips from VME via PCI-3.

To create the hex file that is downloaded over VME do the following.

• After compiling changes to the code: File --> Convert SRAM object
• Select FCF file: Altera\FCF\frc_logic.fcf
  The file order should be (use full pathnames - only shown from Altera\ sub-dir):
  1. trdf\trdf.sof (device = EPC10K50EQC240-1)
  2. bm\bm.sof (device = EPC10K50EQC240-1)
  3. sclf\sclf.sof (device = EPC10K50EQC240-1)
• Output file: ttf\frc_logic.ttf
• Create a hex file from the ttf
  • python ttf2hex.py frc_logic.ttf frc_logic.hex
  • ttf2hex can be found on nevis1 in ~evans/frc_test/frc_bc/firmware
• Make sure that the downloading software (e.g. ~evans/frc_test/frc_bc/frc_config.py) has a reference to the correct hex file.

Option b) - jtag
To load sof files to the three FPGAs using the ByteBlaster do the following.

• Set jtag/prom DIP switches on the FRC to all "0"'s
• Make sure ByteBlaster cable is plugged into FRC Jtag connector.
• Start MaxPlus on desired PC: Max+plusII --> Programmer
• In the Flex menu
  • Make sure Multi-Device Flex Chain
  • Select files: Flex --> Multi-Device Flex Chain Setup
    
    • the (.sof) file order should be the same as above
• Turn on crate.
• Click on Configure
  • If everything is ok - the message "3 devices configured" should appear
  • If the configuration fails during the verification step try reseating the FRC.

BC Firmware

There are three options here.

1. This firmware is burned onto a prom that is soldered onto the BC from which it is loaded into the two BC FPGA's at power-up. (See BC Layout for locations.)
2. The firmware is loaded to the prom over the PCI-3 bus, using the Jtag lines connected from the bus to the prom. This is only possible on BC's that have been modified to allow this option.
3. The firmware is loaded to the two FPGAs using the Jtag connector on the BC via a ByteBlaster connection.

Option a) - pre-programmed proms
To create the pof files to be loaded on the proms do the following.

• After compiling changes to the code: File --> Convert SRAM object
• Select FCF file: Altera\FCF\bc.fcf
  The file order should be (use full pathnames - only shown from Altera\ sub-dir):
  1. BC\Buf_Ctrl\bc_ctrl.sof (device = EPC10K30EQC208-1)
  2. BC\PCI3\bc_pci3.sof (device = EPC10K50EQC240-1)
• Output file: pof\bc.pof (device = EPC2LC20 - note not default)
• Burn the prom: EPC2LC20
• Solder prom to BC
• Set jtag/prom DIP switches to all "1"'s

Option b) - re-program proms over PCI
Create the jbc file to be loaded to the prom over the PCI-3 bus connection to the prom's Jtag lines.

• Create a single .pof file containing bc_ctrl and bc_pci3 as described in option a) above.
  When compiling add the following steps:
  • Assign --> Global Project Device Options

    Use Low-voltage Configuration Device	checked
    Configuration Device	EPC2LC20
    Use Configuration Device Pull Resistor	checked

• After compiling the code:
  • Max+plus II Menu --> Programmer (ignore message about no programmer hardware)
  • File --> Create JAM or SVF file
• Select JCF file: Altera\JBC\bc.jcf
  The file order should be (use full pathnames - only shown from Altera\ sub-dir):
  1. pof\bc.pof (device = EPC2)
• Output file: pof\bc.jbc (device = EPC2LC20 - note not default)
  • Choose the output format in the "File format" pull down menu.
    This must be .jbc (Jam STAPL Byte Code 2.0) If you don't choose 2.0, the software won't work (I know, I've done it...)
• Load the code to a prom on a BC: from a VxWorks terminal
  • at Nevis this is d0vmecpu1
  • all commands below assume that the BC to be programmed is in VME slot 13
  • At the -> prompt type the following:
    jbirun(13,"-cBUFC", "-aPROGRAM","yourfilename.jbc",1)
  • Note: make sure that yourfilename.jbc exists in the directory in which the VxWorks terminal ends up in after startup.
  • You will get some error msg when jbirun is finished, this is a problem they are trying to fix, but it's won't affect the jtag program by all means, so just ignore it for the time being.
• Other jbirun commands
  • jbirun(13,"-cBUFC", "-h","yourfilename.jbc")
    It will show you jbirun usage. 13 is the slot #.
  • jbirun(13,"-cBUFC", "-i","yourfilename.jbc")
    It will show you all the info and all available actions included in your jbc file. Usually the actions include PROGRAM, CONFIGURE, BLANKCHECK, EREASE...We will use PROGRAM.
• Remember that the jtag/prom DIP switches must be set to all "1"'s
• Power cycle the board so that the new code is loaded from the prom. (There is probably a less drastic way to do this.)

Option c) - jtag
To load sof files to the two FPGAs using the ByteBlaster do the following.

• Set jtag/prom DIP switches on the BC to all "0"'s
• Make sure ByteBlaster cable is plugged into BC Jtag connector. The pin-1 position on the cable should face up and out of the crate.
• Start MaxPlus on desired PC: Max+plusII --> Programmer
• In the Flex menu
  • Make sure Multi-Device Flex Chain
  • Select files: Flex --> Multi-Device Flex Chain Setup
    
    • choose Restore FCF
    • at Nevis the appropriate FCF can be found in: E:\STT\BC\bc.fcf
    The file order should be (use full pathnames):
    1. bc_ctrl.sof (device = EPC10K30EQC208-1)
    2. bc_pci3.sof (device = EPC10K50EQC240-1)
• Turn on crate.
• Click on Configure
  • If everything is ok - the message "2 devices configured" should appear
  • If the configuration fails during the verification step try reseating the BC.