FRC & BC FIRMWARE MODIFICATION LOG
==================================

Dec-02 Version
--------------
20-Dec  pci3_lt.tdf             o Burst_R uses cben (=l_cmdo[3..0]) = 0xC # 0x6
        (frc & bc)
18-Dec  bm.acf                  o removed pin assignment: SCL_Ready=128
                                  SCL_Ready is a NODE in bm_regs
12-Dec  pci3_lt.tdf             o changed addressing of SR L3 FIFO
05-Dec  bc_pci3.gdf             o changed def of BAR0: FFF00000 to FFF00008
02-Dec  pci3_lt.tdf             o changed addressing for WC and L3 fifos



bm_l2_orig.tdf = bm_l2_0128_nevis.tdf


0122: Hal's changes regarding reset for SLV_RDY


0128: GST  remove  L2_P condition from EN_SLV

> --    IF GETDONE.q[3..0] > SLVRDY.q[3..0] and L2_P then GST 01/28/2003
>       IF GETDONE.q[3..0] > SLVRDY.q[3..0] and SLV_RDYn and SLV_DONEn then



0129_1 : GST changes wrt 0128 (<)

<       ELSIF GETDONE.q[3..0] == SLVRDY.q[3..0] and EN_SLVRDY.q[] then
---
>
>       ELSE
>               EN_SLV          = GND ;
>       END IF ;
>
>       IF GETDONE.q[3..0] == SLVRDY.q[3..0] and EN_SLVRDY.q[] then
344a351,352
>       ELSE
>               GET_Equal = GND;




0129_2 : TRIAL version (set GET_EQUAL always to GND)
This is the ONLY change wrt 0128




0129_3 : Use != instead of > to avoid inconsistency when 4 bit counter overflows
This is the only change wrt 0129_1



0130_1 : set GET_Equal ALWAYS to GND (trial version)
This is the ONLY change wrt 0129_3



0130_2 : set GET_Equal ALWAYS to GND AND EN_SLV ALWAYS VCC (trial version)



0206: changes wrt 0128

-- put GET_Equal through flip flop
-- again: != instead of >= 
-- allow SLV_RDY to be asserted when SLV_DONE is deasserted and  Getdone is deasserted, ie. replace SLV_RDYn --> GET_Donen
-- change condition for GET_EQUAL 
--	ELSIF GETDONE.q[3..0] == SLVRDY.q[3..0] and EN_SLVRDY.q[] then
	ELSIF GETDONE.q[3..0] == SLVRDY.q[3..0] and !SLV_DONEn and !L2_P then 




diff bm_l2_0206.tdf bm_l2_0128_2.tdf


<       IF GETDONE.q[3..0] != SLVRDY.q[3..0] and SLV_DONEn and GET_DONEn then        --GST
<               EN_SLV          = VCC ;
< --    ELSIF GETDONE.q[3..0] == SLVRDY.q[3..0] and EN_SLVRDY.q[] then
<       ELSIF GETDONE.q[3..0] == SLVRDY.q[3..0] and !SLV_DONEn and !L2_P then           --GST



>       IF GETDONE.q[3..0] > SLVRDY.q[3..0] and SLV_RDYn and SLV_DONEn then

>               EN_SLV          = VCC ;
>       ELSIF GETDONE.q[3..0] == SLVRDY.q[3..0] and EN_SLVRDY.q[] then



02xx: Tulika
bm_regs.tdf : add L1_ERROR L1_BUSY L2_ERROR and L2_BUSY to   BM1_Status

0226: Tulika
bm_regs.tdf : remove CPU_ENABLE condition from MON_INTERRUPT and SCL_INTERRUPT




0319:
bm_l1.tdf:
remove Srdy_Req from L1_ENA: allows us to do L1 action while SLV_RDY asserted


0331:
New Altera Megacore



04/01/03 : pci3_lm.tdf (BC)
	 : Set STTL1ERR to GND.
	 : Implement John's latency timer fix.




4/14/03
bm_l1.tdf
Georg go back to L1 period only when SLV_RDY deasserted (undo 3/19 change)


4/15/03:
BC/PCI3/pci3_lt.tdf and bc_pci3.gdf
Georg:     test completion of address phase by lm_tsr[2]


                                                                                              
4/16/03
bm_regs.tdf:
Added L1Busy_PCI3 to BM0Status[31]


4/18/03
bm_test_pins.tdf and bm.gdf
Add 
BM_T2                   = L1_AF_inBM ;
BM_T1                   = L2_AF_inBM ;
NOTE: BM_T1 does NOT work



4/19/03
trdf_format.tdf: Tulika turns off turn number checking

4/21/03
trdf_format.tdf: Tulika turns  turn number checking back on


5/01/2003 ? : PCI_3_FRC.tdf:
protect write counter from overflow.
Don't see "going out of sync" problem anymore

5/6/2003:
bm.gdf, bm_l2.tdf, bm_meout.tdf, bm_l2.sym, bm_meout.sym:
Try to fix race condition by delaying en_sl2

--> Can run for ~134 k events, then out of sync again!
(0 bias run with ~800 HZ/ 330 Hz)


5/7/2003:
PCI_3_FRC/pci3_l3.tdf
fix residual problem in reset of read/ write counters

5/20/03:
BM/bm_meout.tdf, bm_l2.tdf
1) Impose minimum time between Strobe_Message's
   Rules for output strobes are:
   a) For Strobe_M2 arriving shortly after Strobe_M1
      If Strobe_M2 < Strobe_M1 + 6 ==> Strobe_M2 = Strobe_M2 + 6
      (and vice versa)
   b) If Strobe_M2 = Strobe_M1     ==> Strobe_M2 = Strobe_M2 + 6
      (L1 strobes always win the race)
   c) BM_Message[11..0] is valid 1 clock before strobe
   d) BM_Message[11..0] stays vaild until next strobe
2) Note: this allows removing EN_SL2_DELAY added on 5/7