Modification Log
Notes:
| Byte | ||||
| Addr | 3 | 2 | 1 | 0 |
| 0x00 | Device ID | Vendor ID | ||
| 0x04 | Status Register | Command Register | ||
| 0x08 | Class Code | Revision ID | ||
| 0x0C | BIST | Header Type | Latency Timer | Cache Line Size |
| 0x10 | Base Address Register 0 | |||
| 0x14 | Base Address Register 1 | |||
| 0x18 | Base Address Register 2 | |||
| 0x1C | Base Address Register 3 | |||
| 0x20 | Base Address Register 4 | |||
| 0x24 | Base Address Register 5 | |||
| 0x28 | Card Bus CIS Pointer | |||
| 0x2C | Subsystem ID | Subsystem Vendor ID | ||
| 0x30 | Expansion ROM Base Addr Register | |||
| 0x34 | reserved | Cap. Pointer | ||
| 0x38 | reserved | |||
| 0x3C | Max. Latency | Min. Grant | Interrupt Pin | Interrupt Line |
| FRC | BC | ||
| Object | PCI-1,2 | PCI-3 | PCI-3 |
| Device ID | 0x0004 | 0x0004 | 0x0004 |
| Vendor ID | 0x1172 | 0x1172 | 0x2001 |
| Class Code | 0xFF0000 (default) |
0xFF0000 (default) |
0xFF0000 (default) |
| Revision ID | 0x01 | 0x01 | 0x01 |
| Header Type | 0x00 (not bridge) |
0x00 (not bridge) |
0x00 (not bridge) |
| Latency Timer | 0x00 ? | 0x00 ? | 0x00 ? |
| Cache Line Size | written at startup | ||
| Number of BARs | 1 | 1 | 1 |
| BAR0 | 0xFFFF0000 16 bit addr (64kB) |
0xFFF00000 20 bit addr (1MB) |
0xFFF00000 20 bit addr (1MB) |
| Hardwire BAR0 | 0x00000000 (disabled) |
0x3AB00000 (disabled) |
0x47B00000 (disabled) |
| Expansion ROM | disabled | ||
| CIS Pointer | 0x00000000 disabled |
||
| Subsystem ID | 0x0000 | 0x0000 | 0x0000 |
| Subsystem Vendor ID | 0x0000 | 0x0000 | 0x0000 |
| Capabilites List Pointer | 0x40 | 0x40 | 0x40 |
| Max Latency | 34 | 33 | 33 |
| Min Grant | 10 | 8 | 8 |
| Interrupt Pin | 0x00 (no interrupt) |
0x01 (intan implemented) |
0x00 (no interrupt) |
| Feature Enable Bits | 0x00000000 | 0x00000000 | 0x00000000 |
| 66 MHz Capable | no | no | no |
| target Device | EPF10KE50SAQC240-2P | EPF10K50EFC240 | EPF10K50EQC240 |
| Bits | Definition |
| 0 | Memory Indicator 0 = memory 1 = I/O |
| 2..1 | Memory Type 00 = 32-bit address space |
| 3 | Memory Prefetchable 0 = not prefetchable ? 1 = prefetchable ? |
| 31..4 | Number of Address Bits to Decode for this BAR bits set to 1 (counting down from bit 31) are disabled as address bits |
| Bits | Definition |
| all | 0 = disable 1 = enable |
| 5..0 | Hardwire BARn (n=5..0) |
| 6 | Hardwire Exp ROM |
| 7 | Expansion ROM |
| 8 | Capabilities List |
| 9 | CIS Pointer |
| 10 | Interrupt Acknowledge |
| 11 | reserved |
| 12 | Internal Arbiter |
| 13 | Host Bridge |
| 14 | Add Internal Data Steering Logic |
| 15 | disable Master Latency Timer |
| 16 | 64-bit PCI Device |
| 31..17 | reserved |