Modification Log
Notes:
| l_adro bits | Used for | 
| 19..16 | Device (W/R): 0 = FRC general or PCI1,2 1/2 = TRDF 3/4 = SCLF 5/6 = BM 7/8 = PCI3 | 
| 15 | Single or Burst R/W Action 0 = single 1 = burst | 
| 14..12 | Element within device (varies by device) 0 = control(w) or status(r) 1 = parameters(w) 2 = data (single) 3 = varies 4 = data (burst) 5 = commands | 
| Name | Access | PCI Addr[19..0] | Description | 
| General: addr offset from PCI-3 (log3) | |||
| FRC_CTRL | w | 0x0'7000 | FRC data input control | 
| PCI-1:
    addr offset from PCI-1 (log1) (same def's for PCI-2) | |||
| PCI1_T_R | r | 0x0'0F00 | Single Read T/R Data | 
| PCI1_TARGETADD | w | 0x0'5500 | Target Addr for Write to LTB | 
| PCI1_CMND | w | 0x0'7700 | Single Write Command Register | 
| PCI1_STAT | r | 0x0'A000 | PCI-1 Status Register | 
| PCI1_CTRL | w | 0x0'F000 | PCI-1 Control Register | 
| TRDF addr offset from PCI-3 (log3) | |||
| TRDF_CTRL | w | 0x1'0000 | TRDF Control Register | 
| TRDF_PARAMETERS | w | 0x1'1000 | TRDF Parameters | 
| TRDF_SW_TEST | w | 0x1'2000 | Single Write Test Data | 
| TRDF_COMMAND | w | 0x1'5000 | Commands from CPU | 
| TRDF_BW_TEST | w | 0x1'C000 | Burst Write Test Data | 
| TRDF_STAT | r | 0x2'0000 | TRDF Status | 
| SCLF addr offset from PCI-3 (log3) | |||
| SCLF_CTRL | w | 0x3'0000 | SCLF Control Register | 
| SCLF_PARAMETERS | w | 0x3'1000 | SCLF Parameters | 
| SCLF_SW_TEST | w | 0x3'2000 | Single Write Test Data | 
| SCLF_STOP | w | 0x3'3000 | Clear Stop/Repeat | 
| SCLF_BW_TEST | w | 0x3'C000 | Burst Write Test Data | 
| SCLF_STAT | r | 0x4'0000 | SCLF Status | 
| BM addr offset from PCI-3 (log3) | |||
| BM_CTRL | w | 0x5'0000 | BM Control Register | 
| BM_SCL_CMND | w | 0x5'1000 | SCL Init Command Register | 
| BM_MON_CMND | w | 0x5'2000 | Monitoring Command Register | 
| BM_SW_FREE_NO | w | 0x5'3000 | Single Write Free Buffer No. | 
| BM_CRATEID_W | w | 0x5'5000 | Write Crate ID | 
| BM_BW_FREE_NO | w | 0x5'C000 | Burst Write Free Buffer No. | 
| BM_STAT_0 | r | 0x6'0000 | BM Status - word 0 | 
| BM_STAT_1 | r | 0x6'1000 | BM Status - word 1 | 
| BM_L3XFER | r | 0x6'3004 | Read L3 Transfer No. | 
| BM_CRATEID_R | r | 0x6'2008 | Read Crate ID | 
| PCI-3 addr offset from PCI-3 (log3) | |||
| FRC_RES | w | 0x7'0000 | Software System Reset | 
| PCI3_CONF_SW | w | 0x7'1000 | Single Write Configuration Data | 
| PCI3_RECONF | w | 0x7'2000 | Enable Reconfig of Logic Elements | 
| PCI3_CMND | w | 0x7'3000 | Command Register | 
| PCI3_CONF_BW | w | 0x7'8000 | Burst Write Configuration Data | 
| PCI3_CONF_STAT | r | 0x8'0000 | Configuration Status | 
| PCI3_L3_DAT_SR | r | 0x8'2000 | Single Read L3 Data | 
| PCI3_MON_DAT_SR | r | 0x8'3000 | Single Read Monitoring Data | 
| PCI3_L3_DAT_BR | r | 0x8'8000 | Burst Read L3 Data | 
| PCI3_MON_DAT_BR | r | 0x8'9000 | Burst Read Monitoring Data | 
| l_adro bits | Used for | 
| 31..16 | Required to be the same for WC and L3 Data by SBC VME addressing restrictions. | 
| 15..0 | Required to be non-zero for WC address by SBC. Can be zero for L3 Data address. | 
| 19..14 | Bit pattern 1001'01 is reserved
                 for use by L3 Output FIFO burst read (corresponds to 0x94000 - 0x97FFF) | 
| 19..16 | Element Number: 0-6 = write 8-9 = read | 
| 15..12 | Single/Burst L3 Read 0 = not L3 Data 1 = single 2 = burst | 
| 11..8 | null | 
| 7..4 | Action 0 = control(w) 1 = data(w) 8 = data(r) | 
| 3..0 | Target values = 0,4,8,C | 
| Name | Access | PCI Addr[19..0] | Description | 
| BC addr offset from PCI-3 (bc) | |||
| BC_CTRL | w | 0x0'0000 | BC Control Register | 
| BC_TARGET_ADDR | w | 0x1'0004 | Target Addr for L3 Data Read | 
| BC_SCL_CLEAR | w | 0x2'0008 | Clear SCL Init Status Register | 
| BC_SOFTWARE_RST | w | 0x3'000C | Software System Reset | 
| BC_SW_RST_FIFO | w | 0x5'0014 | Reset Word Count FIFO | 
| BC_STATUS | r | 0x8'0080 | BC Status | 
| BC_BR_L3 | r | 0x9'4000 - 0x9'7FFF | Burst Read L3 Output FIFO 16,384 bytes | 
| BC_WC_READ | r | 0x9'8F00 | Read Word Count FIFO | 
| BC_SR_L3 | r | 0x9'8F08 | Single Read L3 Output FIFO |