===================================================================================================== FRC STATUS INFORMATION: CRATE: d0olstt00 SLOT : 13 Fri Mar 5 21:33:30 2004 ===================================================================================================== TRDF STATUS REGISTER ===================================================================================================== bb NAME REF E/W VAL || bb NAME REF E/W VAL ===================================================================================================== 02 TRDF STARTED 1 - 1 || 03 START TEST 1 - 1 04 TEST MODE 0 - 0 || 05 TEST_REPEAT 0 - 0 06 RR_FIFO_EMPTY 1 - 1 || 07 RR_FIFO_FULL 0 - 0 08 RR_FIFO_FULL LATCHED 0 E=1 0 || 09 BX MISMATCH ERROR 0 W=1 0 10 TURN MISMATCH ERROR 0 W=1 0 || 11 BOE MISSING ERROR 0 W=1 0 12 EOE MISSING ERROR 0 W=1 0 || 13 NO CTT DATA 0 E=1 0 16 RR SM IDLE 1 - 1 || 17 RR_DATA LATCH 0 - 0 18 RR_DATA_WRITE 0 - 0 || 19 RESERVED 0 - 0 ===================================================================================================== SCLF STATUS REGISTER ===================================================================================================== bb NAME REF E/W VAL || bb NAME REF E/W VAL ===================================================================================================== 00 START RUN 1 - 1 || 02 SCLF STARTED 1 - 1 03 START TEST 1 - || 04 TEST MODE 0 - 0 05 LIMITED TEST MODE 0 - 0 || 06 SCL_SYNC_ERROR 0 E=1 0 07 SCL_MEZZ_DATA_ERR 0 E=1 0 || 08 SCL_MEZZ_READY 1 - 1 ===================================================================================================== PCI1 STATUS REGISTER ===================================================================================================== bb NAME REF E/W VAL || bb NAME REF E/W VAL ===================================================================================================== 01 START_PCI12 1 - 1 || 02 TEST_MODE 0 - 0 03 TIMEOUT ENABLE 1 - 1 || 04 TIMEOUT LATCH 0 E=1 0 05 L1 FIFO EMPTY 1 - 1 || 06 L1 FIFO FULL 0 E=1 0 07 L1 IDLE 1 - 1 || 08 LM_CHECK 0 - 0 09 EOE_PCI_33 0 E=1 0 || 15 BLANK 0 - 0 10-15 T/R Word Count 00 - 00 16-27 PCI 1 Time Out Data 00 - 00 ===================================================================================================== PCI2 STATUS REGISTER ===================================================================================================== OPTION STATUS OPTION STATUS ===================================================================================================== 01 START_PCI12 1 - 1 || 02 TEST_MODE 0 - 0 03 TIMEOUT ENABLE 1 - 1 || 04 TIMEOUT LATCH 0 E=1 0 05 L1 FIFO EMPTY 1 - 1 || 06 L1 FIFO FULL 0 E=1 0 07 L1 IDLE 1 - 1 || 08 LM_CHECK 0 - 0 09 EOE_PCI_33 0 E=1 0 || 15 BLANK 0 - 0 10-15 T/R Word Count 00 - 00 16-27 PCI 2 Time Out Data 00 - 00 ===================================================================================================== PCI3 STATUS REGISTER ===================================================================================================== bb NAME REF E/W VAL || bb NAME REF E/W VAL ===================================================================================================== 00 l_CONF_DONE 1 - 1 || 01 l_nCONFIG 1 - 1 02 l_nSTATUS 1 - 1 || 03 MON_FIFO_EMPTY 1 - 1 04 MON_FIFO_FULL 0 - 0 || 05 L3_IN_IDLE 1 - 1 06 WRITE_FIFO_DATA 0 - 0 || 07 WRITE_WORD_COUNT 0 - 0 08 WRITE_CHECKSUM 0 - 0 || 09 L3_OUT_IDLE 1 - 1 10 FIRST_WORD_LATCH 0 - 0 || 11 BR_FIFO 0 - 0 12 BR_END 0 - 0 || 13 SR_FIFO 0 - 0 14 MASTER_WAIT 0 - 0 || 15 END_WAIT 0 - 0 29 L3 FIFO EMPTY 1 - 1 || 30 L3 FIFO FULL_ERR 1 - 1 24-27 # Evts in FRC-PCI3 FIFO 00 - 00 ===================================================================================================== BM STATUS REGISTER 0 ===================================================================================================== bb NAME REF E/W VAL || bb NAME REF E/W VAL ===================================================================================================== 00 PUT_DONE_WAIT 0 - 0 || 01 START BM 1 - 1 02 SOFTWARE TRIG DMA (no SBC) 0 - 0 || 03 GET_DONE_WAIT 0 - 0 04 GET_ALL_WAIT 0 - 0 || 05 SLV_DONE_CHK 0 - 0 06 SLV_DONE_END 0 - 0 || 07 MON IN PROGRESS 0 - 0 08 MON DONE 0 - 0 || 09 SLAVE READY 0 - 0 10 MON INTERRUPT 0 - 0 || 11 SCL REQ 0 - 0 12 SCL DONE 0 - 0 || 13 SCL INIT ACK 0 - 0 14 SCL INTERRUPT 0 - 0 || 15 PUT_DONE TIMEOUT 0 E=1 0 16 GET_DONE TIMEOUT 0 E=1 0 || 17 PUT_ALL_WAIT 0 - 0 28 L1 FIFO FULL 0 E=1 0 || 29 L2 FIFO FULL 0 E=1 0 30 L3XFER NUMBER FIFO FULL 0 E=1 0 || 31 PCI3 L3 FIFO FULL 0 E=1 0 ===================================================================================================== BM STATUS REGISTER 1 ===================================================================================================== bb NAME REF E/W VAL || bb NAME REF E/W VAL ===================================================================================================== 12 L1 BUSY 0 E=1 0 || 13 L2 BUSY 0 E=1 0 14 L1 ERROR 0 W=1 0 || 15 L2 ERROR 0 W=1 0 16 PUT DONE 0 - 0 || 17 PUT DONE# 1 - 1 18 GET DONE 0 - 0 || 19 GET DONE# 1 - 1 20 STT_L1BUSY# 1 - 1 || 21 STT_L2BUSY# 1 - 1 22 STT_L1ERROR# 1 - 1 || 23 STT_L2ERROR# 1 - 1 24 BM_L1_BUSY 0 - 0 || 25 BM_L2_BUSY 0 - 0 26 XFER_IN_ERR 0 - 0 || 27 XFER_OUT_ERR 0 - 0 28 OVERFLOW_ERROR (L1) 0 E=1 0 || 29 OVERFLOW_ERROR (L2) 0 E=1 0 30 OUTPUT FIFO FULL (Latched) 0 E=1 0 || 31 VOID 0 - 0 ===================================================================================================== LRB status (mip6) CSR: 003f1260 Status register: 0040490e Receiver counters Channel Words Blocks Fixed Error ID Err Fifo 0 65542 21841 0 0 0 9 1 0 0 0 0 0 0 2 0 0 0 0 0 0