The home page of     Dr. Jaroslav Bán

"I have seen the travail, which God hath given to the sons of men to be exercised in it. " Ecc 3:10

Recent projects

Since 2008 i am working on the development of ADC for the Liquid Argon Electronics upgrade of the Atlas experiment at LHC (Cern, Geneve, Switzerland).

Here you can find more information about the project.

LARTDS16 chip

LARTDS16 chip is designed to collect the data from 4 Nevis ADC chips and send them to Atlas Larg trigger system. The chip performs this using 2 serializers working at 4.8 GHz. .

CAD picture of the chip die is here.

NEVISMUX15 chip

NEVISMUX15 chip is an interface chip designed to connect 2 Nevis ADC chips to Cern GBT chip .

CAD picture of the chip die is here.

NEVIS14 and NEVIS15 chips

NEVIS14 and NEVIS15 chips fix bugs found in NEVIS13 and add new features to the ADC .

The size and silicon sizes stay the same as in NEVIS13.

NEVIS13 chip

NEVIS13 chip represents 4 full 12bit ADC channels .

Picture of the chip die is here.

My talk about the project at Cern is here.

Some info about the performace of developed ADC is here.

NEVIS12 chip

NEVIS12 chip (in the test board socket) represents 2 full 12bit ADC channels. Each channel consist of 4-bit MDAC pipeline and 8-bit SAR.

Picture of the chip die is here.

NEVIS10 chip

NEVIS10 chip (in the center of the test board) represents another step toward ADC as it consist of 2 full 4bit ADC with gain selector structures in front of each ADC.

Layout of the chip is here.

NEVIS09 chip

With NEVIS09 chip we wanted to test the technology (IBM 8RF 130nm), tools and the options at the transistor level we have to build basic building blocks of the ADC (Operational Transimpedance Amplifier and Sample/Hold circuit).

The chip layout is here.