Data Routing on the SLIC Links

Version 4:
01-May-02
- corrected ordering of bits in link-word (Format of data transmitted on link) to reflect FPGA code (see slic_link_lnk.tdf)
24-Jan-02
- changed F-bit definition using correct L1Quals
- added check on ForcedWrite bit in L1 Quals

Types of Data Transmitted over Links

Data	Source	Destination	V[5..1]	F
Trigger Data (inp:0)	SCL via MBT	all DSPs(1-5)	11111	x
Input Data (inp:1-15)	Muon System	any comb(1-4)	0xxxx	0
Input Mark & Pass	Muon System	5 + any comb(1-4)	0xxxx	1
Processed Data	DSP-n(=1-4)	DSP-5	10001 10010 10100 11000	x
Output to Hotlink	5	Hotlink Out	00000	x
Invalid	n.a.	n.a.	10111 11101 11011 11110 10011 11001 10011 10110 10101 11010	x

Notes:

x = either 0 or 1 allowed
V[5..1] = DSP routing bits
F = Full Readout bit
Processing DSPs = 1-4
Formatting DSP = 5

Format of Data Transmitted on Links

Bits	Name	Description
38	C	End of Data Block
37	P	Valid Data Word
36-32	V[5..1]	Director Bits for DSPs
31-0	DAT[31..0]	Data

Additional Routing Control Generated in DSP5 FPGA

Full-Readout Bit (F):
F=1 is set in DSP-5's FPGA if the most recent trigger data is flagged as full readout (L2UnbiasedSample or L2ForcedWrite) in the L1 Qualifiers:

F=1 if V[5..1]=11111 & (L1QUAL[0]=1 or LIQUAL[3]=1)
Note: L1QUAL is in 4th word from channel 0
F remains 1 until next V[5..1]=11111 (trigger) word arrives
The check on L1QUAL[0] is then redone to set F=0,1

The F-bit is unaffected by DSP output data being interleaved with the input channel data. This is because input channel data has V[5]=0 (except for channel 0) while DSP output data has V[5]=1

Delta-Bit (D):
D=1 if the Director Bits of the current link word are different from those of the previous link word:

D=1 if Vnew[5..1] != Vold[5..1]

Note: this bit is only used internally by the DSP-5 FPGA.

Loading Link Data to DSP FIFOs

The DSP FPGAs determines whether a give word is to be sent to its DSP FIFO based on a comparison between the routing bits (V[5..1]) transmitted with the data on the link and a look-up-table loaded into the FPGA (N[4..0]). As words are accepted by the FPGA and loaded into the fifo they are counted in the variable sercount.

Rules for DSP 1-4's FIFOs:

Link words are loaded to DSP-n FIFO (n=1-4) if and only if bit V[n]=1
Then set sercount = sercount+1

Rules for DSP 5's FIFO:

If V[5]=1: Link word is always loaded to DSP-5 FIFO
If V[5]=0: Link word is loaded to DSP-5 FIFO if Full Readout (mark-and-pass) bit is set (F=1) for the current input event.
Then set sercount = sercount+1

Notes:

Input Data (V[5]=0) for Event i always arrives after Trigger Data for Event i and before Trigger Data for Event i+1. Processed Data has V[5]=1 and only one V[n]=1 - so cannot be confused with Processed, Input or Trigger Data. Therefore, there is no possibility to confuse DSP-5 into loading input or processed data as full readout for an incorrect event.

The DSP FPGA Stack

Data is loaded from the fifo sitting on the DSP's input port under control of the DSP FPGA Stack. Fifo reads to the DSP are initiated by sending a word to the DSP on its serial input port. This word is called the "Stack Word". Formats for the Stack Word DSPs 1-4 and DSP 5 can be found in The DSP FPGA Stack.

Processing FPGA/DSP Rules

FPGA 1-4 Rules:
For any link word that satisfies the criteria for being loaded to the DSP FIFO the Stack Word is written to the DSP input serial port if:

C=1 or O=1
Then set sercount=0

DSP 1-4 RULEs:
On receipt of a stack word on its serial input port, the processing DSPs perform one read from the FIFO to the appropriate internal input buffer (see Memory Management in the DSPs)

Read sercount+1 words to current input buffer
Update current input buffer

Formatting FPGA/DSP Rules

FPGA 5 Rules:
For any link word that satisfies the criteria for being loaded to the DSP FIFO the Stack Word is written to the DSP input serial port if:

C=1 or O=1 or D=1
Then set sercount=0

DSP 5 RULEs:
On receipt of a stack word on its serial input port, the formatting DSP compares Vold and Vnew and checks the F-bit and then writes data to the appropriate internal data buffer(s) (see Memory Management in the DSPs)

If Vold = Vnew

Read sercount+1 words to buffer pointed to by Vold or F

If Vold != Vnew

Read sercount words to buffer pointed to by Vold or F
Read 1 word to buffer pointed to by Vnew or F

Glossary of Terms

new	refers to the current word on the link
old	refers to the previous words from the link
sercount	counts words from link to DSP fpga (sercount in the FPGA code)
F	the Full Readout flag
V	the link word routing bits (valin[5..1] in the FPGA code)
N	Bits Loaded into DSP FPGA used to recognize correct V-bit (Look-Up-Table or N[4..0] in the FPGA code)
D	change of director bits flag (DSP5 only) (delta in the FPGA code)
O	word count overflow (sercount=255) (srovf in the FPGA code)
C	last word in event flag (X[1] in the FPGA code)
P	valid data word (X[0] in the FPGA code)
Stack Word	sent by FPGA to DSP serial to initiate reading of fifo

DSP-5 Examples

Old			New				DSP Reads
cnt	FDOC	V[5..1]	FDOC	V[5..1]	cnt	Stack Word	from FIFO
C-Bit & O-Bit Changes
i	x000	10001	x000	10001	i+1	n.a.	n.a.
i	x000	10001	x001	10001	0	Vold,Vnew,CF,0,O,i	i,1
255	x000	10001	x010	10001	0	Vold,Vnew,CF,0,O,255	255,1
0	x010	10001	x000	10001	1	n.a.	n.a.
0	x010	10001	x001	10001	0	Vold,Vnew,CF,0,O,0	0,1
0	x001	10001	x001	10001	0	Vold,Vnew,CF,0,O,0	0,1
D-Bit Changes
i	x000	10001	x10x	10010	0	Vold,Vnew,CF,0,O,i	i,1
0	x100	10010	x000	10010	1	n.a.	n.a.
0	x1xx	10010	x10x	10001	0	Vold,Vnew,CF,0,O,0	0,1
255	x000	10001	x11x	10010	0	Vold,Vnew,CF,0,O,255	255,1

Notes:

The F-Bit does not cause a stack word to be loaded to the DSP. It is used here to direct data within the DSP to the Full-Readout Buffer.
The D-Bit is not written with the stack word. It is the responsibility of DSP-5 to reconstruct it from Vold and Vnew.