DSP Serial Output Data Format

In order to properly mark the last word in data blocks on the link when performing transfers from the processing DSPs (1-4) to the Formatting DSP (5) and from Formatting DSP to the Output FPGA it is necessary to add additional information to the DSP serial output. We have chosen to do this by appending an extra 8-bit control byte to each 32-bit data word transmitted out of the DSPs on their serial ports. In the DSP operating system, this is accomplished by doing a DMA transfer of five bytes for each 32-bit data word to be transferred out. The DSP FPGA uses the Control Byte to generate a C-bit on the link, marking the last word in a data block, for the data word associated with it.

This scheme has the drawback that it slows down the DSP output, which is already a bottleneck in the system, by a factor of 4/5. However, no other prospects for data output that preserve the block structure appear to be possible.

The format of the output data is shown below.
Byte Bits Description Memory
4 7-0 Control Byte
=0: normal data
=1: end of block
Hi Mem
3 31-24 Data Byte 3 (MSB)  
2 23-16 Data Byte 2  
1 15-7 Data Byte 1  
0 7-0 Data Byte 0 (LSB) Lo Mem