The DSPs can be controlled and tested by sending commands to them (on Serial Port 1) from VME through the DSP FPGA. DSP commands are sent to the DSP FPGA as 8-bit data and are flagged with the appropriate DSP FPGA command so that they will be sent to the DSP serial port in stack word format but with bit 9 set to indicate that the accompanying byte is a command and not a link word count.
A list of valid commands as implemented in boot36 is given below.
| No. | Name | Description |
| 1 | TEST_SBRAM | Loads SRAM with 64k words (0 - 0x10000), reads them back and compares with the expected values |
| 2 | TEST_FIFO1 | Reads previously loaded (by driver code) data pattern from DSP FIFO and compares with expected values |
| 3 | TEST_FIFO2 | same as test_fifo1 but different pattern |
| 4 | TEST_FIFO3 | same as test_fifo1 but different pattern |
| 6 | LOADMEM |
Reads previously loaded (by driver code) block of data from FIFO
to DSP memory using DMA.
Returns (on serial output to VME) a checksum calculated on the
data (currently not working).
Order data should be loaded in FIFO by driver is:
|
| 10 | VME_OUT | Ouput on DSP serial port will go to VME |
| 11 | LINK_OUT | Output on DSP serial port will go to the link |
| 13 | CIRC_SETUP | Circulation Test setup information ready to be read from DSP FIFO |