SLIC Test Modes

A list of the main test modes implemented in boot36/SlicDrive is given below. Those marked with a * are run automatically. The others are selectable from the SlicDrive menu.

Data Flow Tests Loop Tests Circulation Tests
BIST Mode Tests Boot Tests*



Data Flow Tests

In this set of tests data is loaded (from VME) at various points in the system and then released to flow through the links into the DSPs and out to VME.

The user selects:

  1. the input channel(s) to use (before entering the data flow test section)
  2. the DSP(s) to use (before entering the data flow test section)
  3. the number of events
  4. the number of words per event
  5. the storage mode in the DSP
    In the current code only mode 0 (load a full data block into memory and then send it out) is implemented.
Words in each event increment from 0 and are marked with the event number (and input number if appropriate) in their higher order bits. Event boundary control information is included with the data. An Input FPGA trailer word is added to the end of each event in tests 3 and 5 (since they skips the Input FPGA).

Data flow test modes (selected from the SlicDrive menu) are given below.

Mode Description
1 Output FIFO --> Input --> Link --> DSP(s) --> VME
• This requires a cable to be connected from the output to the selected input
3 Input FIFO(s) --> Link --> DSP(s) --> VME
• No cable is required in this test.
• If input channel 0 is not selected, mock trigger data is created and loaded to the channel 0 FIFO so that readout can occur.
5 Input FIFO(s) --> Link --> DSP --> Link --> DSP --> VME
• No cable is required in this test.
• If input channel 0 is not selected, mock trigger data is created and loaded to the channel 0 FIFO so that readout can occur.
Loop Tests

This test is similar to the data flow test 3 except that multiple DSPs are used. The data flow is:

Circulation Tests

This test simulates the flow of data through the SLIC over extended periods of time. One data block is sent

for a preset number of loops. Expected and received data is compared in the DSP for each loop and a count of the number of corrupted words recieved is kept. Note that if the DSP code detects a corrupted data block, it sends out the correct version for the next loop so that the error count does not accumulate unecessarily. The error count is sent back to the driver code at the end of the test.

The user enters

  1. the DSP to use (before entering the test)
  2. the number of loops desired
  3. the number of words in the data block
Only input channel 0 can be used to receive data from the output. A cable must be connected between the output and this channel.

The test returns (via the output serial port and VME)

  1. the error count
  2. the last data block stored in DSP memory
  3. the last data block as it would have been sent to the link

BIST Mode Tests

BIST mode is implemented both on the Input and Output FPGAs and is selectable by setting the appropriate bit in the FPGA's control register. The BIST Test implemented in SlicDrive sets the output and all selected inputs to BIST mode. Note: both input cypress receivers are set to BIST mode when the A-side of the FPGA is put in BIST. Setting the BIST bit in the B-side has no effect.

When in BIST mode the Input FPGAs keep track of receiver errors and successful data cycles in the ERROR_COUNT (8-bit) and EVENT_COUNT (16-bit) counters. These two counts are not perfectly synchronized and they (especially) the error counter can wrap around quickly. Care should therefore be taken in interpretting the results of the BIST test. The event counter should be used mainly to determine if the receiver is actually getting data, while the error counter should be read as "zero", "a few" or "many" errors.

With no modification to the code, the following conditions can be tested

  1. Standalone Mode: connect the SLIC output to an input
  2. SLIC output to another board: ignore inputs
  3. External source to SLIC input: connect the external source to one of the SLIC inputs

Boot Tests*

These tests are performed at the end of the DSP boot process and are designed to verify the functionality of the DSP.

  1. test_togl: toggles the flag_i and flag_o (serial port 0) lines used for serial output handshaking
  2. test_ser: writes a word out on serial port 1
  3. readregs: sends the contents of all DSP registers out as words on serial port 1