During data transfers into and out of the DSPs' serial ports, handshaking is necessary between the DSP and the data source/destination because the serial ports can only buffer two 32-bit data words. (See the TI C6000 Peripherals Reference Guide for details.) Note that serial input and output of data is only performed on serial port 1 (MCBSP 1). Serial Port 0 (MCBSP 0) is configured at boot-up to perform general purpose I/O and is used as the main vehicle for handshaking. Handshaking is performed in three different situations depending on the direction of the serial data (input/output) and its destination for output (the link or VME).
All handshaking is most directly performed between the DSP and its DSP FPGA. However, in the case of transfers to VME, DSP FPGA handshaking lines are made available to the driver code (SlicDrive) by being part of the DSP FPGA Status Register. It is the driver code that then controls the setting and resetting of the lines that are DSP inputs. Handshaking LinesAll lines between the DSP and DSP FPGA used for handshaking are part of the DSP MCBSP 0, which is configured at boot-up to interpret its serial data and control lines only as general logic inputs and outputs and not as a serial port (general purpose I/O). Pin assignments and definitions of handshaking lines are given below. All DSP pins can also be found in the MCBSP0 Pin Control Register (PCR).
| FPGA pin |
DSP pin |
DSP inp/out |
H'shake with |
Description |
| Serial Output | ||||
| flag_o | fsxp | inp | VME | Handshake to DSP for VME xfers |
| flag_i | fsrp | out | VME | Handshake from DSP for VME xfers |
| data_rdy | clkrp | inp | FPGA | =1: DSP FPGA ready to accept data from DSP |
| Serial Output | ||||
| dsp_rdy | dx_stat | out | FPGA | =1: DSP ready to accept serial input =0: FPGA inhibited from sending to MCBSP 1 |
The DSP is responsible for informing the FPGA when data could overflow its input buffer. Since the buffer is only two words deep, this can happen quite quickly. The serial input section of the DSP operating system is therefore designed to drop dsp_rdy (inhibiting any serial input on MCBSP 1) whenever it is reading, or even checking for the presence of, data. The inhibit sequence implemented in the the DSP OS is given below. (See the TI C6000 Peripherals Reference Guide for details of the serial port.) Note that this sequence is based on the polling version of the input memory management.
| Step | DSP Action | Consequence at FPGA |
| 1. | Set dsp_rdy=0 | No more data will be sent to serial port |
| 2. | Check RRDY bit in MCBSP 1 • =0: no data present • =1: data present |
|
| 3.a | RRDY=0 (no data) • set dsp_rdy=1 • return to 1. |
FPGA can now send data to serial port |
| 3.b | RRDY=1 (data) • set error if MCBSP 1 full (RFULL) • read data to input buffer • perform analysis • return to 1. |
FPGA still inhibited |
The format of data written by the DSP to the serial output is described elsewhere.
During some steps in its parallelization of the serial data received from the DSP serial output, MCBSP 1, the FPGA cannot accept another data word. It signals this condition by setting the data_rdy line to zero. The DSP serial output code must check this line before sending out any data, regardless of the final destination of that data. It also checks internally to make sure that the serial output is ready for data transfer and that the output buffer is also empty. Steps in the process in the DSP code are given below.
| Step | DSP Action | FPGA Condition |
| 1. | DSP wants to write a serial word | |
| 2. | Check XRDY & EMPTY bits (MCBSP 1) wait if XRDY=0 or EMPTY=1 |
|
| 3. | Check value of data_rdy | =0: FPGA busy with previous word =1: FPGA ready for data |
| 4.a | data_rdy=0 (busy) • wait for data_rdy=1 • write word to serial out • return to 1. |
FPGA finishes with the previous word |
| 4.b | data_rdy=1 (ready) • write word to serial out • return to 1. |
Both the DSP and the FPGA need to know, for each output serial word, whether its destination is the link or VME. This is accomplished in the DSP using a global variable set by commands to the DSP and in the FPGA by two bits in the Status/Control Register set by the driver code. In normal running conditions the DSP and FPGA are configured to send serial output data to the link. Care should be taken if this is changed (for testing or monitoring purposes) because the change is a slow process, asynchronous with data flow.
Given below are the states of the DSP global variables and FPGA status bits for link and VME data transfers.
| Data Dest. | DSP Variable | FPGA Status Bits |
| Link | out_to_vme=0 | send2olinkreg=1 send2vmereg=0 |
| VME | out_to_vme=1 | send2olinkreg=0 send2vmereg=1 |
When data is written from a DSP to VME, additional handshaking, beyond that required for a transfer to the link, is necessary. The DSP must be informed that the VME destination (the driver code) has actually received the word and is ready for a new one before it can do another write.
| Step | DSP Action | Driver Action |
| 1. | DSP waiting | Driver wants to read from DSP • sets flag_o=1 (to DSP) |
| 2. | DSP wants to write a serial word • wait for XRDY & XEMPTY • wait for flag_o=1 (from driver) • set flag_i=1 (to driver) • wait for data_rdy (from FPGA) |
Driver waiting for transfer |
| 3. | DSP writes word | Driver waiting for transfer |
| 4. | DSP waits | Driver receives word • set flag_o=0 (to DSP) |
| 5. | DSP acknowledges • wait for flag_o=0 (from driver) • set flag_i=0 (to driver) • ready for next write |
Driver waiting for ack |
| 6. | DSP ready | Driver finishes • wait for flag_i=0 (from DSP) • ready for next read |