Initialization/Synchronization of ADF to TAB Data Transfer

updated: 01-Dec-04

Index

Initialization/Synchronization of Data Transfer
The Synchronization Mechanism
BC and TURN number Synchronization
Errors & Resynchronization
Version 1 (25-May-04)

Initialization/Synchronization of Data Transfer

The initialization and synchronization scheme for ensuring that ADF data is correctly received at the TABs has been considerably simplified compared to the previous version of the firmware.

In the new scheme:

The phase of the serial ADF data stream is determined by a frame bit which is transmitted simultaneously with data-bit 0 (the LSB).
Synchronization is based on comparing the BC numbers received as part of the ADF data with those calculated in the TAB based on SCL signals.
SCL Init is not required to start this process, although it will reset the synchronization.

The Synchronization Mechanism

Event synchronization is ensured by writing/reading to/from a DPRAM in the SW chips using an address derived from a truncated version of the BC number received from the ADF (write) and generated in the TAB based on SCL signals (read). Only the lowest three bits of the BC number are used when generating the write/read address because only a few BC's are required to do the synchronization. Using the full 8-bit BC number would substantially increase the size of the DPRAM without any benefit.

Action address[5..3] address[2..0]

Write ADF_BC_number[2..0]
(from ADF input data) bit number of data (0-7)
(this is generated by a 3-bit counter clocked at 60 MHz)

Read TAB_BC_number[2..0]
(reconstructed from SCL signals) bit number of data from DPRAM (0-7)
output data bits 8-11 are added to the end of this stream, set to 0
(generated by a 4-bit counter clocked at 90 MHz)

A block diagram of the synchronization scheme is shown below. (A ps version is available here.)

Error Checking and Resynchronization

Mismatches between BC numbers received in the ADF data and the BC number regenerated in the TAB are flagged in the Global chip on the TAB.

Action	address[5..3]	address[2..0]
Write	ADF_BC_number[2..0] (from ADF input data)	bit number of data (0-7) (this is generated by a 3-bit counter clocked at 60 MHz)
Read	TAB_BC_number[2..0] (reconstructed from SCL signals)	bit number of data from DPRAM (0-7) output data bits 8-11 are added to the end of this stream, set to 0 (generated by a 4-bit counter clocked at 90 MHz)