SCL Signals Used by the TABs, GAB & VME/SCL

updated: 01-Dec-04

Index


SCL Signals

See also Serial Link Receiver Specifications

Signal In/Out Used By Comments
SCL_ACK Out VME/SCL In reset
SCL_READY In VME/SCL valid trigger/timing info
SCL_SYNCERROR In VME/SCL  
SCL_DATAERROR In VME/SCL  
CLK_53 In VME/SCL Main clock - always present
CLK_7 In VME/SCL,GAB,TAB BC clock - only on valid data
 
CURRENT_TURN[15..0] In [gen] Turn Number - this period
CURRENT_BX[7..0] In [gen] Crossing Number - this period
FIRST_PERIOD In GAB,TAB 1st period in turn
BEAM_PERIOD In VME/SCL Period with beam marker
SYNC_GAP In GAB No L1 Accepts
Used for sync of signals to TFW
COSMIC_GAP In   Only Cosmic triggers
SPARE_PERIOD In    
 
L1_PERIOD In VME/SCL L1 Accept this period
L1_ACCEPT In GAB,TAB L1 Accept this geographic section
L1_ACCEPT & L1_PERIOD is sent
L1_TURN[15..0] In [stored] Turn Number - L1 Accept
L1_BX[7..0] In [stored] Crossing Number - L1 Accept
L1_QUAL[15..0] In GAB Only CollectStatus bits
L2_PERIOD In   L2 decision this period
L2_ACCEPT In   L2 Accept this geographic section
L2_REJECT In   L2 Reject this geographic section
 
INIT_SECTION In GAB,TAB Initialize
L1_BUSY Out VME/SCL Sending data to L2
L2_BUSY Out    
L1_ERROR Out GAB Request initialization
L2_ERROR Out    
INIT_ACK Out VME/SCL Acknowledge init request
SYNC_LOST Out VME/SCL  
SPARE_STATUS[1..0] Out    


SCL Data to the TAB

Transmission of the necessary subset of SCL timing and control signals to the TAB is made via the VME/SCL Interface board (VME/SCL) using LVDS protocol with 6 data pairs. A similar cable and connector is used for this transmission as is used for ADF-to-TAB data transmission. The only difference is that three 5-pin rows are used for the VME/SCL data rather than four 5-pin rows for the ADF-to-TAB cables.

The GAB uses as similar set of signals. To be added...

Pair Name Description
1 clk7 SCL CLK7
2 init initialize request
3 turn SCL FIRST_PERIOD
4 l1_accept SCL L1_PERIOD & L1_ACCEPT
5 pulse used for L1Cal-internal sync pulse
6   spare


Generating BC & TURN

Bunch Crossing (BC) numbers corresponding to the BC in which the data was actually produced in the calorimeter are transmitted along with the TT Et's from the ADF. Click here for details. Note: this BC is several (need to specify this exactly) ticks earlier than the BC/TURN currently being sent on the SCL.

BC and TURN numbers are generated in the TABs and GAB from CLK_7 and FIRST_PERIOD signals. They must be synchronized to the BC expected from the ADFs in order to allow data synchronization checks and to correctly mark data in the SYNC_GAPs for use by the TFW and Cal-Track system.

The following algorithms are used to achieve this synchronization.

BX Counter   8-bit (1:159)
incremented on:   CLK_7
reset to 1 when BC=160
reset to BC0(ADF) by FIRST_PERIOD
reset to 0 by INIT_SECTION
TURN Counter   16-bit
incremented on:   FIRST_PERIOD + N ticks
reset to 0 by INIT_SECTION

Notes:


Storing BX & TURN for L2/L3 Readout

BX and TURN numbers generated for the bunch crossing in question are stored with the L2/L3 data in a fixed depth pipeline. L1_ACCEPT is used to transfer this data to the L2/L3 buffer.


L1 Qualifiers

Bit Name HW/Std Used by L1Cal
00 L2ForcedWrite Std no
01 L2GlobalNeeded Std no
02 L2MuNeeded Std no
03 L2UnbiasedSample HW no
04 L2EmNeeded Std no
05 L2JetNeeded Std no
06 L2EtMissNeeded Std no
07 CollectStatus HW Yes - Collect monitoring data
08 L2PSNeeded Std no
09 L2TrackNeeded Std no
10 L2ImpactNeeded Std no
11 reserved HW  
12   Std  
13   Std  
14 L2STTNeeded Std no
15 reserved HW  
  1. HW or Std refer to "hardware" type or "standard" type qualifiers.
  2. A Standard L1_Qualifier is asserted for a given event if any one of a defined subset of the 128 L1 Specific Triggers fired for that event. The "defined subset" of L1 Specific Triggers for each of the 12 Standard L1_Qualifiers is setup by COOR at the COOR to Trig FW trigger download time, i.e. their meaning is dynamic and can be moved by COOR to fit the user's requirements.
  3. A Hardware L1_Qualifier is asserted if its electrical input control signal is asserted. These are hard wired so they can not be moved about by COOR.