ADF to TAB Cabling

updated: 29-Nov-06

Index

• Mapping of Channels to Physical Eta
• ADF Channel Link Signal Connections to a Single TAB SW Chip & notes
• Bit Stream Mapping on Channel Link Cable
• TAB Sliding Windows Chip Input Channel Map
• Cable/Connector Spec's & Diagrams
• Transmission Speed
• Proposal from 8-Jan-03 (for reference)

• BLS inputs to ADFs
• Channel mapping in the TABs, M.Mulhearn (20-Oct-05)

Notes:

1. Relative TT Numbering
   The 32 TTs seen by an ADF are numbered as two (EM and HD) 4x4 arrays in [eta x phi] with:
   • eta: 0-3
   • phi: 0-3
2. ADF Outputs
   • Each SW chip on a TAB receives input from three ADFs (i-1, i, i+1)
   • Each ADF sends out three identical copies of the data on its 32 channels on cables A, B, C to three different TABs.
   • Outputs with numbers in italics and with white backgrounds are connected at the TABs, but not used by SW chip shown in this example.
3. Cable Pairs
   
   • Cable pairs numbered: 0-6 + clk
   • Bits in each pair numbered: 0-6
     bit-6 used for DC-balance
4. Sliding Window (SW) Chip
   • There are 10 SW chips on each TAB (0-9). Only one is shown in this example.
   • E = EM signal used in sliding windows algo. (0-80)
   • H = HAD signal used in sliding windows algo. (0-80)
   • ADF outputs that are not used in the sliding window algorithm are connected to the SW chip but not passed forward.
5. BC
   • The bunch crossing number corresponding to the BC when the Et's reported above were actually deposited in the calorimeter.
6. History
   • Currently unused
   • Could be used to mark special data transfers.
7. Parity
   • Parity on each of the ADF's output cables is calculated using all of the data on that cable, whether it is used in the sliding windows algorithm or not.
8. n.c. = not connected

Notes:

1. See National DS90CR483 / DS90CR484, 48-Bit LVDS Channel Link SER/DES spec sheet

TAB Sliding Windows Chip Input Channel Map (EM & HD)

Notes:

1. Each SW chip (j)on a TAB receives input from:
   • three input cables from three different ADFs: i-1, i, i+1
   • two other SW chips: j-1, j+1 (via connections on the TAB)
2. In eta x phi space the 9x9 EM and 9x9 HD TTs inputs break down as follows:
   • ADF i-1: 4x2
   • ADF i: 4x4
   • ADF i+1: 4x3
   • SW Chip j-1: 3x9
   • SW Chip j+1: 2x9
3. Numbering Convention
   • SW Chip Inputs used in sliding windows algo: 0-80
   • SW Chip inputs not used in sliding windows algo: not numbered

Connector & Cable Diagrams

• ADF to TAB cable path - through the transition system Paddle Card
• Cable and Connector Diagrams at the Boards
  • ADF end
  • TAB end
  • Note: the pin column labeling convention used in the L1Cal diagrams above is opposite to that used in the AMP cable spec given below: i.e. column A in the L1Cal diagrams corresponds to column E in the spec.
• TAB/GAB Backplane Connections

Cable Specifications

• Parts list for TAB Cables & Connectors
• Gore Z-Pack 2mm HM Cable Connector assemblies: 2MMS02xx
• Connector on TAB & GAB: AMP 106012-1
• Connector on TAB/GAB crate Backplane: AMP 223071-2
• Shroud for Backplane Connector: AMP 223041-2
• Old AMP Cables/Connectors
  • Cable: AMP 621410-6 (photo)
  • Connector Family: AMP Z-Pack 2mm HM

Transmitters & Receivers

• Channel Link Serializer/Deserializer: DS90CR483/4 Spec Sheet

Tests of the Cables

• Transmit/Receive Tests at Nevis: Jovan's talk at the Nov-02 Saclay Workshop

LVDS Clock Speed

• f(clock) = (7 streams/cable) x (8-bits/stream) / 132 ns = 424 MHz
• f(data)  = (6 streams/cable) x (8-bits/stream) / 132 ns = 364 MHz

Data Transmission Rate

• 1 ADF to TAB: R(ADF) = (7 cables) x f(data) = 318 MByte/s
• 30 ADFs to 1 TAB: R(TAB) = (30 ADF-cables) x R(ADF) = 9.5 MByte/s
• 240 ADF cables to 8 TABs: R(tot) = (240 ADF-cables) x R(ADF) = 76 GByte/s