VME Communication with the TAB & GAB

updated: 19-Sep-03

VME Interface Card

VME accesses to the TABs and GAB are made via the VME Interface board (VMEI) that translates VME addresses and data to serial data sent to the TABs and GAB on separate cables consisting of 6 data pairs using LVDS protocol. A similar cable and connector is used for this transmission as is used for ADF-to-TAB data transmission. The only difference is that three 5-pin rows are used for the VMEI data rather than four 5-pin rows for the ADF-to-TAB cables.

VME Access

Addressing

Bits Name Description
23..19 ga[4..0] VME slot address
18..15 module[3..0] Module in TAB crate
  • TAB = 0-7
  • GAB = 8
14..11 chip[3..0] Chip on Module
  • TAB: SW-chip = 0-9; Global-chip = 10
  • GAB:
10..07 group[3..0] memory group
06..04 sub[3..1] reserved for sequences to reduce latency

VME Writes

VME write operations are translated to serial data to the TAB or GAB being addressed using the following scheme.
  1. MOD[3..0] --> Select serial output number
  2. CHIP[3..0] --> Frame (ser_frm_in)
  3. D[31..16] --> Memory address in chip (ser_addr_in)
  4. D[15..0] --> Data to write (ser_data_in)

VME Reads

Reads of data stored in the TABs or GAB are accomplished by writing (as above) to specified addresses in a chip. If the address requested corresponds to a valid read location, the chip responds by presenting a 16-bit data word (ser_data_out) and frame (ser_frm_out) to an output register. The contents of this register, which is cleared upon each VME write operation, are sent to the serial output of the module in question when a valid frame is received.

VME Memory Maps


Serial Transfer Definition

Pair Name Description
1 ser_clk clock for serial transmission
2 ser_frm_in frame & destination chip for writes
  • 15:      frame signal (=1)
  • 14..11 CHIP[3..0]
  • 10..00 unused
3 ser_addr_in address in chip for input data (16-bit)
4 ser_data_in data to TAB (16-bit)
5 ser_frm_out marks 1st bit of 16-bit output data
6 ser_data_out data from TAB (16-bit)

Transfer Speed

The LVDS serial lines will run at 15 MHz. The limit is actually from the data bus to the FPGAs on the TAB. This means that typical transfer times will be:
Transfer Size Total Time
Firmware Download ~6 MBytes/chip ~10 sec
TAB Online Monitoring
16-bit Sum(Et) and Sum(Et2) for each TT		 1280 Bytes/TAB ~5.5 ms