TAB I/O Tests

Index

In the following, the tests that have been done on the various TAB input and output chains are described. The goal of these tests is to convince ourselved that the TAB hardware will not require any modifications to make the board work as specified. When appropriate, we point out what tests remain to be done to achieve this goal. All of the remaining tests should be accomplished within the next few weeks.

Data Transfer from the ADF
Data Transfer to the GAB
Data Transfer to the Cal-Track system
Data Transfer to L2/L3
Communication with VME & SCL

Data Transfer from the ADF

This transfer is accomplished using the Channel Link chipset's implementation of the LVDS protocol. The link runs at 424 MHz, well below the Channel Link maximum spec. More details are available here.

Tests Done so Far

Fall 2002:
Effects of the cables that will be used in the final system as well as studies of Channel Link parameters for both transmission and reception have been studied using a test card at Nevis. More details are available from Jovan's talk at the Nov-02 Saclay Workshop.
No bit errors were observed for a wide range of parameters at the 10^-14 level.
Fall 2003:
A few events at a time of data from ADF test memories were transmitted from the ADF to the TAB using timing from the TFW. Correct data was verified by hand by reading out the TAB input memories.
Fall 2003:
Pseudo-random data from the ADF test memories was transmitted to the TAB on up to three channels at Fermilab using timing from the TFW. No errors were observed on ADF channels not affected by digitization noise in tests of approximately 15 minutes.

Remaining Tests to Verify the Hardware

None.

Data Transfer to the GAB

This transfer is accomplished using the LVDS transmitters and receivers built into the Alter Stratix chips on the TAB and GAB. The link runs at 636 MHz, well within the Altera LVDS spec. More details are available here.

Tests Done so Far

October 2003:
Stratix LVDS parameters for transmission and reception were studied using a test card at Nevis. Error-free transmission was achieved for a wide range of parameter values.
March 2004:
Transmission of several events worth of data from 2 TABs to the prototype GAB was tested and found to work.
April 2004:
Long term data transmission tests between a single TAB - repeating 32 events loaded into the TAB's test memory - and the GAB are ongoing. Bit error rate measurements of the transmission should be available soon.

Remaining Tests to Verify the Hardware

Get bit error rates for TAB-to-GAB transmission.

Data Transfer to the Cal-Track System

This transfer is accomplished using the University of Arizona L1Muon Serial Link Daughter Board. It was tested during the fall integration test using L1Muon trigger cards that use identical hardware to that foreseen in the Cal-Track system.

Tests Done so Far

October 2003:
Correct timing of Syn-Gap signals to the L1Muon Serial Link Receiver on the L1Muon trigger card was verified on the scope. Getting this timing right has historically been the main hurdle to overcome in getting this data transmission to work.
October 2003:
While there is no mechanism in the L1Muon cards for examining data transferred to the cards, we did load known patterns into the TAB test memory (i.e triggerable 1 electron per 32 events, 2 triggerable electrons per 32 events) and observed consistent changes in L1Muon trigger rates. We also verified that these triggers occurred in the correct timing bin.

Remaining Tests to Verify the Hardware

None.

Data Transfer to L2/L3

This transfer is accomplished using optical fibers running the HP G-link protocol. Identical data is transmitted to L2 and L3 via an optical splitter (such as the one used in the STT system). Tests have been done transmitting data to VRBs in the existing L1Cal system.

Tests Done so Far

March 2004:
Single events worth of data were transmitted from the TAB test memories to the L1Cal VRB using timing from the TFW. Data quality was verified by hand by dumping the VRB inputs to a file.
April 2004:
Three events in succession (with no SCL inits required between them) worth of data were transmitted from the TAB to an L1Cal VRB using TFW timing. Again data was verified by hand. Data transfer was limited to three events because no trigger configuration file was created with the new input included.

Remaining Tests to Verify the Hardware

Apr/May 2004:
A trigger configuration file will be created that will allow us to write test data from the TAB to tape as part of a special run.

Communication with VME & the SCL

This communication is accomplished using a custom protocol with the VME/SCL card. Details are linked off of the L1Cal Hardware Page.

Tests Done so Far

May 2003 on:
VME access to the TAB (and GAB) has been extensively used during all of the tests of the board.
October 2003 on:
The SCL interface of the VME/SCL card has been used throughout the tests at Fermilab with timing and control data from the TFW. All required functionality has been tested.
March 2004: The local oscillator on the VME/SCL card, used for standalone testing, was replaced with a stabler one to allow tests of G-Link data transfer without TFW timing to be performed.

Remaining Tests to Verify the Hardware

None.