Structure of the FRC and BC Firmware

Updated: 12-June-03

INDEX

  1. Modification Log

  2. Fiber Road Card

  3. Buffer Controller

FIBER ROAD CARD FIRMWARE
BM/bm.gdf Diagram (20-May-03)
bm_l1.tdf Provide the Level 3 Buffer Managment for L1 period.
bm_l2.tdf Provide the Level 3 Buffer Managment for L2 period.
bm_meout.tdf Provide the control of BM's Message output to BCs.
bm_mon.tdf Generate the Monitoring data of BM, store the data into registers.
bm_regs.tdf There are three main functions in the BM_Regs part of Buffer manager:
  1. To receive the Control commands and setting values from VME CPU (via PCI BUS), and keep status Information of Buffer Manager element.
  2. Process the Monitoring interrupt request and SCL Init interrupt request. send the necessary Mon and SCL Command to other elements.
  3. Output Status and Monitoring Data to PCI 3 FPGA.
bm_scl.tdf Receive the SCL Trigger data from SCLF. BM_SCL classes them as three Groups, L1 trigger data, L2 trigger data and L3 Transfer Number. Stores each group data into individual FIFO.
SCLF/sclf.gdf Diagram (20-May-03)
sclf_logic.tdf Receives the SCL data from SCL mezzanine board, Select the available information from the data, divide them as different groups and send them to TRDF and BM for further processing. SCLF_Logic will make monitoring data according to the input SCL data. Several control signals will be generated in the SCLF_Logic used for latching SCL data in the TRDF and Buffer Manager.
test_data.tdf A read and write control circuit of the SCL test data.
TRDF/trdf.gdf Diagram (20-May-03)
trdf_format.tdf Combines SCL & Road information together, reformats them to form a single data block -- T/R Data. Before the formatting processing, BX and TURN number of SCL and CTT data are checked. If any mismatched no is found, the processing will be stoped and L1_ERR message will be sent to SCL Hub.
trdf_mon.tdf Generates the Monitoring data of TRDF, store the data into registers and internal memory, and send the data to PCI 3 FPGA according to collect monitoring data bit of SCL_QUAL[15..0].
trdf_regs.tdf Receives the Control commands and setting values from VME CPU (via PCI BUS), and give status Information of TRDF element.
trdf_rr.tdf Receives the CTT Road information data from VTM. Combines two 16 bits road data into one 32 bit T/R Data with 4 Control bits, and to keeps them in a FIFO of RR.
trdf_scl.tdf Receives and registers the L1_PERIOD information data from SCLF element, and make the Header and Trailer of T/R data, Header of L3 data.
PCI_1/pci_1.gdf Diagram (20-May-03)
lm_logic.tdf lm_logic is a control logic circuit used for the local side of PCI master interface (PCI bus 1 & 2) which gives a PCI block data transfer (burst master write) to several LVDS transmitter boards. This circuit will combine with the MegaCore (pci_mt32) to form a whole PCI master control logic for FRC.
The circuit consists of several parts:
  1. The functions of lm_req32n & lm_redyn are to generate individually the local bus request signal and local ready signal for the local side of PCI interface.
  2. lm_lastn is used for give a local last data signal (lm_lastn) for the local side of PCI interface. lm_lastn is generated after get EOE signal of the T/R Data from FIFO.
  3. lm_adi_cbeni is used to generate local 32 bits address/data and local 4 bits command/byte enable data. it uses lm_adr_ackn & lm_ackn signals to select both of 32 bits address/data bus and 4 bits command/byte enable bus. 32 bit Target address is a constant depend on the PCI address assignment in the system initilization. 32 bits data is from the output of input FIFO.
  4. Input FIFO is used to store the T/R data from TRDF, write control signal is from TRDF and read control is from local logic: EN_R_iFIFO.
lt_logic.tdf A control logic circuit used for the local side of PCI target interface (PCI bus 1 & 2) which give a PCI data transfer (Sigle Read) to check the T/R data of iFIFO.
There are two main functions in the lt_logic.
  1. To provide the local Target single read control for the data transfer of T/R data to CPU to via PCI Bus 1.
  2. To provide the local Target single write control for writing the control register
PCI_3_FRC/pci3_frc.gdf Diagram (20-May-03)
pci3_cf.tdf Local control of Altera chip Configuration for other logic elements. The configuration mode is Passive Serial (PS) with a microprocessor. PCI3 FPGA works as a microproceesor in this mode. It gets a configuration file from CPU via the PCI bus 3, converts data to serial bits from byte_wide parillal data. isses the nCONFIG command, DCLK clock and Data0 to other logic elements, and also monitors nSTATUS and CONF_DONE signals in order to complete the PS configuration.
pci3_l3.tdf Formats L3 data based on the T/R data which is input from TRDF with L3 Header. PCI3_L3 addes L3 Trailer (L3 WC & Checksum) into L3 data stream. L3 data will be save into L3 FIFO according to the Full_Readout message of L1_QUAL[15..0], and be sent to Buffer Controller via PCI Bus 3.
pci3_lt.tdf The main functions of PCI3_lt:
  1. Local control of PCI_Target interface - provides the local control for altera's MegaCore (pci_mt32) target function, it includes:
    - Single write and read.
    - Burst write and read (Read L3 data with Target disconnet function).
  2. Send command and data to each logic element - decodes PCI commands and data, Translate, and send them to each element.
  3. Status report - provides the status of PS configuration of other three Altera FPGA Chips to CPU.
pci3_mon.tdf Accepts Mon data from each element of FRC, store them into a FIFO, and output them to PCI BUS 3 according to the command of Buffer manager.

BUFFER CONTROLLER FIRMWARE
BC/buf_Ctrl/bc_ctrl.gdf Diagram (20-May-03)
b_ctrl.tdf There are two main functions in the B_Ctrl part of Buffer controller:
  1. To provide the data transfer control from L3 Buffers to Output FIFOs according to BM Message of L2 period, Check If the L2 Event No and Checksum are correct.
  2. Reformat the L3 data, make new word count and new checksum for L3 data
BC/buf_Ctrl/bc_pci3.gdf Diagram (20-May-03)
pci3_lm.tdf There are two main functions in the PCI3_lm part of Buffer controller:
  1. To provide the local master burst read control for the data transfer of L3 data from FRC or daughterboard (DB) via PCI Bus 3.
  2. L1_Period Logic control of Buffer Controller. It includes exchange of messages with Buffer Manager of FRC, receive L3 data from DB, check L1_BX No. and store L3 data to L3 buffer (Dual_Port RAM) according to the PUT_BUFF No of Buffer manager.
pci3_lt.tdf There are two main functions in the PCI3_lt part of Buffer controller:
  1. To provide the local Target single & burst read control for the data transfer of L3 data to SBC via PCI Bus 3.
  2. To provide the local Target single write control for some VME commands which inluding SCL_Ready, write Control register and Write Target address to BC