SECOND LEVEL INPUT COMPUTER OVERVIEW

The DØ Level-2 Trigger Muon Preprocessor System (L2MU) is described in detail in the L2MU TDR. The system will be housed in two 9U VME for Physics (VIPA) crates in the DØ movable counting house (MCH). The main components of the system are listed below.

• CIC (cable input converter): These cards transform input data from the muon front ends and the muon Level-1 trigger system to unshielded twisted pair cables used by the SLIC. They reside in their own crate(s).
• SFO (serial fanout): This card (one per L2MU crate) fans out DØ trigger information from the Serial Command Link (SCL) that is received by the MBT.
• SLIC ( second level input computer): These custom-built cards (7 in the "forward" crate and 11 in the "central") function as pre-pre-processors. They receive up to 15 input signals plus SCL data and condense/process/reformat it into output suitable for the Alphas.
• MBT ( magic bus transciever): Among many other functions, these cards (two per crate?)
  • receive SCL information and broadcast it to the SLICs
  • receive the SLICs' output and send it to the Alpha(s) over the magic bus.
• Alpha ( custom-built DEC Alpha-based processor): These cards (one "Administrator" and one "Worker" per crate) receive SLIC data over the magic bus (via the MBT) and construct muon track candidates. These are then sent to the Global Level-2 trigger processor (via the magic bus and MBT).
• Bit3: A dual-port memory and VME interface to an external computer (PC).
• VBD ( vme buffer/driver): The interface with the Level-3 DAQ.

A detailed block diagram of the SLIC is available. It has five main logical elements.

1. Input Sections:
   Input data is received in serial format over unshielded twisted pair cables in Cypress Hotlink format. Space for 16 separate input channels is provided on 8 RJ-45 connectors. This data is received and formatted by 8 Input FPGAs, dealing with two channels each and is stored temporarily in 16 (8K x 36-bit) Input FIFOs.
2. Data Link:
   Data is moved from the inputs to the processing elements over a high-speed point-to-point link that transfers data and destination information for each channel.
3. DSP Daughterboards:
   Processing of the input data is done in four DSPs, connected to the Link and configured at initialization to accept data from specific input channels. These DSPs, along with associated control logic and utilities, are mounted on removable daughterboards which plug into the SLIC motherboard. A fifth DSP (mounted on its daughterboard) collects the results of the four processing DSPs and organizes them into a form usable by the Alpha processor.
4. Output Section:
   Data is sent out (to an MBT) over unshielded twisted pair cables using the Cypress Hotlink protocol. Identical outputs can be driven onto two pairs on a single RJ-45 connector: one is transformer coupled while the other (selectable by jumpers) is not. The output process is controlled by two Output FPGAs connected to the end of the Link.
5. VME Interface:
   For purposes of dowloading, testing and monitoring, VME access is possible to most of the elements of the SLIC.

Data arrives on the SLIC inputs at 16 MBytes/sec from three different sources:

1. The Trigger Framework distributed over the Serial Command Link (SCL) which is recieved by the Magic Bus Transciever (MBT) and sent to the SLICs on channel 0. This data contains information about the L1 and L2 trigger decisions.
2. The L1 Muon Trigger
via a Cable Input Converter (CIC).
3. The Muon Detectors themselves again via a CIC. (See DØ Note 3537 for details of the data formats.)

Data input to the SLIC is accomplished physically by unshielded twisted-pair cable and RJ-45 connectors. Two pairs are active in each connector making a total of eight RJ-45 input connectors. Numbering conventions for the input channels are described elsewhere.

The data from each channel is recieved by Cypress Hotlink Receiver chips which send 8 bits at a time to an Input FPGA (Altera Flex 6000) servicing two channels simultaneously. The FPGAs are programmed to respond to Cypress special characters as specified in the L2 standard. They perform several functions.

1. They direct the data from each channel to a separate (8k x 36-bit) FIFO for buffering.
2. They create a trailer word that is added to the end of the input's data block and contains information about the data.
3. They mark valid data words and the last word in an event block with control bits.

The endianess of the input data received by the hotlinks can be selected by setting a register in the Input FPGA.

3.2 The Link

Data is transmitted within the SLIC over a custom point-to-point link. This data path is 39 bits wide and runs at 40 MHz. Beside a 32-bit data word, it contains event structure and destination information. A hold line is implemented to ensure that data is not lost if an upstream section of the link is busy.

The link consists of two sections.

1. Input Section:
   This consists of 8 FLEX 6000 FPGAs that gather data from pairs of input FIFOs in order starting from channel 0 and ending with channel 15. Any channel except channel 0, which always carries trigger information from the SCL, can be software configured at initialization to be skipped in this readout chain. The channel being read out is controlled by a token, which is passed from channel to channel and finally sent back to channel 0 when an entire event has been read out. Data mut be present on channel 0 before the readout process can begin. Data is sent from the input section link to the DSP-1 FPGA.
   The input section links are responsible for controlling where the data is sent by adding director bits to each data word signalling which DSP(s) it should go to. These director bits are downloaded into each FPGA from the driver code as part of its initialization and are the same for every word coming from that input.
2. DSP/Output Section:
   This is used in sending data from the processing DSPs (1-4) to the formatting DSP (5) and from the formatting DSP to the output buffer. It is implemented as part of the DSP FPGAs and the Output Buffer FPGA. As a consequence, data can only be sent to the SLIC output if all DSP daughterboards are plugged in to the motherboard.

The upper four DSP daughterboards (DSPs 1-4) are responsible for processing data from the event. They have four elements.

1. DSP FPGA:
   This FPGA performs many functions during normal data taking.
   1. It receives and sends link data and holds based on the data's director bits.
   2. It sends data to the DSP FIFO and counts the number of words in each input source block.
   3. It sends a stack word to the DSP's input serial port whenever it encounters a C-bit in the link data to signal that the DSP can read a data block from the FIFO. These stack words are stored in a 16-deep buffer in the DSP FPGA. Note that this does not mean that 16 events are buffered because a stack word is generated for each input data block, of which there are several per event for each DSP.
   4. It interprets the DSP serial output data and generates link C-bits for DSP data blocks.
2. DSP FIFO:
   This 8k x 36-bit FIFO is used to store data from the link while the DSP is busy.
3. SRAM:
   This 64k x 32-bit SRAM is used as extra memory for the DSP.
4. DSP:
   We use a TI fixed point DSP with 64k of program and 64k of data memory as the processing engines in the SLIC.
   The main I/O elements of the DSP used are:
   • Serial Port 0 (MCBSP-0). This is configured for general purpose I/O and used for handshaking serial data transfers on port 1.
   • Serial Port 1 (MCBSP-1). The input port is used to read the stack word from the DSP FPGA. The output is used to send data to the link (or VME).
   • The Data Port. This 32-bit wide port is connected to the FIFO and the SRAM and is used for data and external memory accesses.
   The code running in the DSP has five basic functions and is contained in one executable downloaded at DSP boot-up.
   1. A basic boot kernel
   2. Input, output and utility functions
   3. An input data buffering scheme
   4. Physics algorithms that do the event processing depending on the inputs selected for this DSP
   5. Testing functions to check the DSP at boot-up and on command.

The lowest DSP daughterboard (DSP 5) collects processed data from DSPs 1-4 and formats it for use by the Alpha processor. It may also construct monitoring data that it gathers from DSPs 1-4. Its architecture is identical to that of DSPs 1-4 except that it uses a larger FPGA.

DSP 5's job is complicated by the fact that data arrives at it in an almost random order - both in terms of sources and events. This is described in detail elsewhere. Briefly, several conditions can cause data interleaving.

1. DSPs 1-4 can be processing different events.
2. A DSPs data can break onto the link while another DSP is busy sending its data.
3. On unbiased events, all input data is also sent to DSP 5. This can be mixed up with the DSP 1-4 data.

Formatted data from DSP 5 is sent over the link to the output buffer FPGA which stores it in an 8k x 36-bit FIFO. An output FPGA reads this FIFO and sends two identical copies of the data to two hotlink transmitters - one (the default) that is transformer coupled, and another (jumper selectable) that is not. L2 standard conventions are used for Cypress special characters.

The endianess of the output data sent to the transmitters is selectable by setting a register in the Output FPGA.

The output of these transmitters is placed on two unshielded twisted pair cables connected to a single RJ-45 connector.

VME access to the SLIC is implemented as programmed I/O. The SLIC does not have any VME-mapped memory. The SLICs are programmed to respond to VME cycles with address modifier lines set to AM5-AM0=011011b. Specific SLIC cards are identified using geographic addressing in the SLIC crates with address lines A22-A18 specifying the slot address. Commands are sent to the SLIC on VME address lines A17-A06. Read and write operations are selected by the /WR line (/write).

Serial connections are provided to Input, Output and Link FPGAs and to the DSP FPGAs on the SLIC. These are used by the VME-command FPGA to send commands to the FPGAs and receive back data. Commands, with their corresponding data, fall into several categories.

1. Downloading code to the FPGAs (input and link).
2. Configuring the FPGAs' functionality once their code is downloaded.
3. Reading status registers in the FPGAs.
4. Loading data to FIFOs through their associated FPGAs.
5. Sending commands to the DSPs (via the DSP FPGA connection to the DSP serial port).
6. Enabling/disabling token passing.
7. Initiating resets.
8. Controlling the front-pannel LEDs.

SLIC boards are initialized, configured and tested under the control of external driver code running on a PC (SlicDrive). This code performs the following functions.

1. Downloads code to the Input and Link FPGAs. The VME, DSP and Output FPGAs get their code from eproms. More details are available elsewhere.
2. Loads DSP boot code to the DSP FIFO and boots the DSPs.
3. Allows the choice of various system tests.

SlicDrive will serve as a basis for the SLIC part of the L2Muon DAQ software.